The present invention relates to an information processing system, and more particularly, to an information processing system having a memory controller which can control a memory unit in accordance with the performance of memory elements mounted therein.
Generally, an information processing system employs a DRAM (Dynamic Random Access Memory) element, an SRAM (Static Random Access Memory) element and so on as memory elements which constitute a storage device of the system. In recent years, SDRAM (Synchronous DRAM) and SSRAM (Synchronous SRAM), which operate in synchronism with a clock signal, are also used in wide applications. Memory elements have been improved in access speed and memory capacity in the last several years, and their prices also vary along with the improvements. A system such as an information processing system must be designed such that it can support future elements in order to maintain a long product lifetime. For this reason, an information processing system comprising a storage device generally has a register for determining an operation timing in a memory controller in order to support a plurality of kinds of elements. An operation timing value is set in the register in accordance with the type and operating speed of a particular element, causing the memory controller to output a control signal in accordance with the set value. In addition, the memory controller provides an extra address signal for possible expansion of the memory capacity.
In recent years, information processing systems tend to be required to have an increasingly larger memory capacity, so that it is necessary to not only employ the recent possible memories providing the largest possible capacity and the highest possible speed but mount memory elements as many as possible. However, an information processing system comprising a large capacity of memory has an increased number of memory elements mounted therein for implementing a large scaled memory unit, resulting in an increase in a spatial extension on the unit and variations from one element to another. Consequently, the information processing system fails to exhibit the actual performance and capability of the elements. As such, an information processing system equipped with a large number of memory elements needs to mount and control the memory elements for accommodating the worst conditions in consideration of the trade-off or compromising between the performance and capacity of the mounted memory elements.
In addition, an information processing system equipped with a large amount of memory elements would encounter a problem if any memory element mounted therein fails. Failures of memory elements may be classified into a completely intermittent fault such as an α-ray fault, and a solid fault, i.e., a completely broken memory element. However, not a few failures of elements result from an insufficient timing margin for a particular parameter when the system is operating at a certain operation timing in an operating environment. Conventionally, such failures of memory elements have not been particularly identified and have been treated as solid failures if the memory elements repetitively fail.
Furthermore, since a high performance information processing system equipped with a large amount of memory elements requires large power consumption, a power save mode such as a sleep mode is provided for pausing the operation of memories when a memory unit is not operated.
JP-A-2-234243 discloses a main storage device which comprises means for identifying whether an access is made to a main storage comprised of DRAMs having a high speed access time or a main storage comprised of DRAMs having a low speed access time to automatically switch the memory access timing in a main storage controller.
As described above, an information processing system equipped with large scaled memory elements requires a fine management for the performance of mounted memory elements in order to ensure the capacity, performance and reliability of the memory elements. Conventionally, however, such an aspect has not been taken into account. Specifically, the information processing system equipped with large scaled memory elements may experience an increase in a spatial expansion of the memory elements in a memory unit due to an increase in the number of mounted memory elements, variations in transfer timing from one memory element to another, increased variations in the actual performance of the memory elements due to different environments such as the temperature in a place in which the system is installed, and a degradation of the actual performance of the memory elements due to aging changes and so on. However, the information processing system does not finely manage the memory elements for accommodating these considerations, and therefore fails to sufficiently make use of the capabilities of the memory elements.